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| STL35NF10 N-CHANNEL 100V - 0.025 - 35A PowerFLATTM LOW GATE CHARGE STripFETTM MOSFET PRELIMINARY DATA TYPE STL35NF10 s s s VDSS 100 V RDS(on) < 0.030 ID 35 A TYPICAL RDS(on) = 0.025 IMPROVED DIE-TO-FOOTPRINT RATIO VERY LOW PROFILE PACKAGE DESCRIPTION This Power MOSFET is the second generation of STMicroelectronics unique "STripFETTM" technology. The resulting transistor shows extremely low onresistance and minimal gate charge. The new PowerFLATTM package allows a significant reduction in board space without compromising performance. PowerFLATTM(6x5) (Chip Scale Package) INTERNAL SCHEMATIC DIAGRAM APPLICATIONS s HIGH EFFICIENCY ISOLATED DC/DC CONVETERS ABSOLUTE MAXIMUM RATINGS Symbol VDS VDGR VGS ID IDM (q) PTOT EAS (1) Tstg Tj Parameter Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 20 k) Gate- source Voltage Drain Current (continuos) at TC = 25C Drain Current (continuos) at TC = 100C Drain Current (pulsed) Total Dissipation at TC = 25C Derating Factor Single Pulse Avalanche Energy Storage Temperature Max. Operating Junction Temperature Value 100 100 20 35 22 140 80 0.64 135 -65 to 150 -55 to 150 Unit V V V A A A W W/C mJ C C (q) Pulse width limited by safe operating area (1) Starting Tj = 25C, ID = 35A, VDD = 50V August 2001 1/6 STL35NF10 THERMAL DATA Rthj-case Rthj-amb Thermal Resistance Junction-case Max Thermal Resistance Junction-ambient Max 1.56 50 C/W C/W ELECTRICAL CHARACTERISTICS (TCASE = 25 C UNLESS OTHERWISE SPECIFIED) OFF Symbol V(BR)DSS IDSS IGSS Parameter Drain-source Breakdown Voltage Zero Gate Voltage Drain Current (VGS = 0) Gate-body Leakage Current (VDS = 0) Test Conditions ID = 250 A, VGS = 0 VDS = Max Rating VDS = Max Rating, TC = 125 C VGS = 20V Min. 100 1 10 100 Typ. Max. Unit V A A nA ON (1) Symbol VGS(th) RDS(on) Parameter Gate Threshold Voltage Static Drain-source On Resistance Test Conditions VDS = VGS, ID = 250A VGS = 10 V, ID = 17.5 A Min. 2 Typ. 2.8 0.025 Max. 4 0.030 Unit V DYNAMIC Symbol gfs (1) Ciss Coss Crss Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Test Conditions VDS =20 V, ID = 15 A VDS = 25 V, f = 1 MHz, VGS = 0 Min. Typ. 18 1780 265 162 Max. Unit S pF pF pF 2/6 STL35NF10 ELECTRICAL CHARACTERISTICS (CONTINUED) SWITCHING ON Symbol td(on) tr Qg Qgs Qgd Parameter Turn-on Delay Time Rise Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Test Conditions VDD = 50 V, ID = 17.5 A RG = 4.7 VGS = 10V (see test circuit, Figure 1) VDD = 80 V, ID = 35 A, VGS = 10 V (see test circuit, Figure 2) Min. Typ. 28 63 60 10 23 80 Max. Unit ns ns nC nC nC SWITCHING OFF Symbol td(off) tf Parameter Turn-off-Delay Time Fall Time Test Conditions VDD = 50 V, ID = 17.5 A, RG = 4.7, VGS = 10 V (see test circuit, Figure 1) Min. Typ. 84 28 Max. Unit ns ns SOURCE DRAIN DIODE Symbol ISD ISDM (1) VSD (2) trr Qrr IRRM Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 18 A, VGS = 0 ISD = 35 A, di/dt = 100A/s, VDD = 25 V, Tj = 150C (see test circuit, Figure 3) 114 456 8 Test Conditions Min. Typ. Max. 35 140 1.2 Unit A A V ns nC A Note: 1. Pulsed: Pulse duration = 300 s, duty cycle 1.5 %. 2. Pulse width limited by safe operating area. 3/6 STL35NF10 Fig. 1: Switching Times Test Circuit For Resistive Load Fig. 2: Gate Charge test Circuit Fig. 3: Test Circuit For Diode Recovery Behaviour 4/6 STL35NF10 PowerFLATTM(6x5) MECHANICAL DATA mm. MIN. A A1 b D D2 E E2 e L 0.65 2.95 1.27 0.85 0.025 3.95 6.00 3.05 0.115 0.049 0.033 0.36 4.89 4.05 0.154 0.235 0.119 0.80 0.08 0.48 0.014 0.191 0.158 TYP MAX. 1.00 MIN. 0.031 0.003 0.018 inch TYP. MAX. 0.039 DIM. 5/6 STL35NF10 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics (c) 2001 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 6/6 |
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